The present invention is generally directed to differential difference amplifiers and, more specifically, to a differential difference amplifier optimized for amplifying a small signal close to zero volts.
In numerous applications, there is need to amplify a small in put signal that is close to zero volts (0V) (or a negative supply voltage) and to add a fixed constant voltage to the result. FIG. 1 illustrates an exemplary battery monitoring circuit 100 in which a small voltage close to a zero volt reference is amplified and offset by a constant voltage. Battery monitoring circuit 100 comprises battery 105, sense resistor 110, scaler 115, analog-to-digital converter (ADC) 120 and load circuit 125. In an exemplary embodiment, load circuit 125 may be a cell phone that monitors battery 105 to determine if battery 105 is charging or discharging and to determine the rate at which battery 105 is charging or discharging.
The battery current generated by battery 105 is sensed over sense resistor 110, which is a very small resistor (about 0.1 ohm). During charging of battery 105, the input voltage to scaler 115 is positive. During discharge of battery 105, the input voltage to scaler 115 is negative. In both situations, the sense voltage is very small (typical range is xe2x88x92100 mV to +100 mV, but xe2x88x9210 mV to +10 mV also is a possible range). This small sense voltage has to be scaled and amplified to a signal that can be used in by ADC 120. Scaler 115 typically amplifies the sense voltage by a factor of 10 or 100 and add the mid-level voltage of ADC 120 to the amplified signal. The digitized sense voltage at the output of ADC 120 is then read by processing circuits in the cell phone (i.e., load circuit 125) to determine the state of battery 105. It should be noted that there are many other applications in which scaler 115 performs a similar amplification and offset function.
Scaler 115 must have a high ohmic input so that a low-pass filter (e.g., a 1M resistor and a 1 xcexcF capacitor) may be added between the sense voltage and scaler 115. In that way, the average battery current can be measured. One approach implementing scaler 115 is to use a standard non-inverting operation amplifier (op amp) having a first resistor, R1, with a first terminal coupled to the negative input of the op amp and a feedback resistor, R2, coupled between the negative input and the output. Two level shifters are used to add a constant voltage (typical half the supply voltage: Vdd/2)) to the positive input of the op amp and to the second terminal of the first resistor, R1. In this approach, the input signal of the op amp is always positive. The transfer function from input to output voltage of such a circuit is:
Vout=Vdd/2+((R1+R2)/R1)Vin
Unfortunately, this approach requires very accurate level shifters. Mismatch and non-linearity in the level shifters directly affects the accuracy of the overall scaling. The level shifters must be able to be used with a high impedance input of the scaler, which reduces the number of possible circuits.
There is therefore a need in the art for improved circuits that are capable of monitoring small voltages close to zero volts (or a negative supply rail). There is a further need for improved amplification circuits that amplify a small input signal close to zero volts (0V) (or a negative supply voltage) and add a fixed offset voltage to the result.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a differential difference amplifier for amplifying an input signal close to a negative supply voltage and adding an offset voltage to the amplified input signal. According to an advantageous embodiment of the present invention, the differential difference amplifier comprises: 1) a first non-inverting input terminal capable of being coupled to the input signal; 2) a first inverting input terminal capable of being coupled to the negative supply voltage; 3) a second inverting input terminal capable of being coupled to a feedback resistor coupled to an output of the differential difference amplifier; 4) a second non-inverting input terminal capable of being coupled to the offset voltage; 5) a first differential transistor pair comprising a first transistor having a gate coupled to the first non-inverting input and a second transistor having a gate coupled to the first inverting input; 6) a second differential transistor pair comprising a third transistor having a gate coupled to the second non-inverting input and fourth transistor having a gate coupled to the second inverting input; 7) a first cascode transistor pair comprising a fifth transistor having a gate coupled to the first non-inverting input and a source coupled to a drain of the first transistor and a sixth transistor having a gate coupled to the first inverting input and a source coupled to a drain of the second transistor; and 8) a second cascode transistor pair comprising a seventh transistor having a gate coupled to the second non-inverting input and a source coupled to a drain of the third transistor and an eighth transistor having a gate coupled to the second inverting input and a source coupled to a drain of the fourth transistor.
According to one embodiment of the present invention, a source of the first transistor and a source of the second transistor are coupled to the output of a first bias current generating source.
According to another embodiment of the present invention, a bulk connection of the first transistor and a bulk connection of the second transistor are coupled to the offset voltage.
According to still another embodiment of the present invention, a bulk connection of the fifth transistor and a bulk connection of the sixth transistor are coupled to the sources of the first and second transistors.
According to yet another embodiment of the present invention, a source of the third transistor and a source of the fourth transistor are coupled to the output of a second bias current generating source.
According to a further embodiment of the present invention, a bulk connection of the third transistor and a bulk connection of the fourth transistor are coupled to a positive supply voltage.
According to a still further embodiment of the present invention, a bulk connection of the seventh transistor and a bulk connection of the eighth transistor are coupled to the sources of the third and fourth transistors.
According to a yet further embodiment of the present invention, a drain current of the fifth transistor and a drain current of the seventh transistor are combined to produce a first composite current.
In one embodiment of the present invention, a drain current of the sixth transistor and a drain current of the eighth transistor are combined to produce a second composite current.
In another embodiment of the present invention, a current difference detection circuit capable of detecting a current difference in the first and second composite currents and generating an output voltage proportional to the current difference.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.